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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRBPIDR2, Peripheral Identification Register 2</h1><p>The TRBPIDR2 characteristics are:</p><h2>Purpose</h2>
        <p>Provides discovery information about the component.</p>

      
        <p>For additional information, see the CoreSight Architecture Specification.</p>
      <h2>Configuration</h2><p>TRBPIDR2 is in the Core power domain.
    </p><p>This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPIDR2 are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>TRBPIDR2 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="24"><a href="#fieldset_0-31_8">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">REVISION</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">JEDEC</a></td><td class="lr" colspan="3"><a href="#fieldset_0-2_0">DES_1</a></td></tr></tbody></table><h4 id="fieldset_0-31_8">Bits [31:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_4">REVISION, bits [7:4]</h4><div class="field">
      <p>Component major revision. TRBPIDR2.REVISION and <a href="ext-trbpidr3.html">TRBPIDR3</a>.REVAND together form the revision number of the component, with TRBPIDR2.REVISION being the most significant part and <a href="ext-trbpidr3.html">TRBPIDR3</a>.REVAND the least significant part. When a component is changed, TRBPIDR2.REVISION or <a href="ext-trbpidr3.html">TRBPIDR3</a>.REVAND are increased to ensure that software can differentiate the different revisions of the component. <a href="ext-trbpidr3.html">TRBPIDR3</a>.REVAND should be set to <span class="binarynumber">0b0000</span> when TRBPIDR2.REVISION is increased.</p>
    
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-3_3">JEDEC, bit [3]</h4><div class="field">
      <p>JEDEC-assigned JEP106 implementer code is used.</p>
    
      <p>Reads as <span class="binarynumber">0b1</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-2_0">DES_1, bits [2:0]</h4><div class="field">
      <p>Designer, JEP106 identification code, bits [6:4]. <a href="ext-trbpidr1.html">TRBPIDR1</a>.DES_0 and TRBPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.</p>
    
      <div class="note"><span class="note-header">Note</span>
        <p>For a component designed by Arm Limited, the JEP106 identification code is <span class="hexnumber">0x3B</span>.</p>
      </div>
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h2>Accessing TRBPIDR2</h2><h4>TRBPIDR2 can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>TRBE</td><td><span class="hexnumber">0xFE8</span></td><td>TRBPIDR2</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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